1. Field of the Invention
The present invention relates to an electronic device including semiconductor electronic elements, and more particularly, to an electronic device having an improved structure for element isolation of electronic elements, a method of isolating elements of the electronic device, a method of producing the electronic device, and a display apparatus including the electronic device.
2. Description of the Related Art
In recent years, in a display apparatus including a display element such as a liquid crystal cell or an electroluminescent element (EL element), there have been used, as electronic elements for driving the display element, multiple thin film transistors (TFTs) which use amorphous silicon, polysilicon, and the like for respective channel regions.
Currently, there is a growing demand for high resolution display apparatuses, for example, a high resolution liquid crystal display device. One of the main factors that inhibit this increase in resolution is the size of each TFT. Further, in order to normally operate the TFTs, the TFTs are required to be electrically isolated from each other. A technology of electrically isolating the electronic elements such as the TFTs from each other is referred to as element isolation. The element isolation of the TFTs is generally realized by patterning respective channel regions of the TFTs into island shapes by using photolithography and dry etching or wet etching so as to be electrically independent from each other.
At present, in the element isolation realized by patterning the semiconductor films of the TFTs into island shapes, the smallest element size may be obtained when dry etching is employed. However, a very expensive vacuum apparatus is used in dry etching, which is a cause of increase in production cost. Further, the size of the semiconductor film is determined not only by the process accuracy of the semiconductor film, but also by considering a contact between the semiconductor film and an electrode. In order to reduce the cost, it is effective to employ wet etching. However, wet etching is lower in process accuracy than dry etching in some cases. Further, in a case where a material which changes its electrical characteristics due to moisture is used as the semiconductor material in the channel region, a certain limitation may be added when finely formed due to the moisture adsorption to the channel region in the wet process or the like, or a throughput may be decreased due to addition of drying process or the like.
Further, as a method of forming independent island-shaped channel regions other than the above, there is a method which uses a shadow mask at the time of film formation for element isolation, but in this case, the process accuracy is further decreased than the case of employing wet etching.
Meanwhile, as a technology of isolating the elements from each other without patterning the semiconductor film into island shapes, there are a method in which a barrier is used for element isolation (Japanese Patent Application Laid-Open No. 2007-220713), and a method in which a semiconductor film in an element isolation region is increased in resistance by doping impurities for element isolation (U.S. Pat. No. 4,962,412).
By the way, the technologies described in Japanese Patent Application Laid-Open No. 2007-220713 and U.S. Pat. No. 4,962,412, in which the semiconductor film is not patterned into island shapes, require forming of the barrier or impurity doping, and hence those technologies do not have advantages in terms of process accuracy compared with the technology in which the semiconductor film is patterned into island shapes. Therefore, there are demands for further improvement in process accuracy when the semiconductor electronic element such as the TFT is finely formed and for reduction in cost.